A memory cell in an integrated circuit (IC) includes a transistor and an associated capacitor. The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates, i.e., electrodes, which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. As the density of the ICs with memory cells is increased, the area for the capacitor becomes smaller and the amount of charge the capacitor is able to accumulate is reduced. Thus, with less charge to detect, reading the information or data from the memory cell becomes much more difficult.
With a limited fixed space or volume for the capacitor of a memory cell in a highly integrated circuit, there are three known techniques for increasing the amount of charge within a fixed space or area. These three known techniques include: (1) decreasing the thickness of the dielectric material, i.e., node dielectric, that is located between the capacitor plates; (2) changing the dielectric material to one with a relative dielectric constant higher than SiO2 or Si3N4; or (3) increasing the surface area of the space to be used for housing the capacitor.
Of the above mentioned techniques, solution (3) is most viable because the other two solutions have several drawbacks associated therewith which limit their use. For example, solution (1), which thins the capacitor dielectric, also increases leakage currents that may affect the memory retention performance of the capacitor and the reliability of the memory cell. Solution (2), which purports to change the dielectric material to a higher-dielectric constant material, will only cause a slight improvement in charge storage because the dielectric constant of suitable alternative dielectrics is only slightly higher than the dielectric material currently being used. Moreover, the substitution of alternative dielectrics may be more complicated, more expensive and provide fabrication problems that are heretofore unknown.
Accordingly, solution (3), i.e., increasing the surface area of the space to be used for the capacitor, provides the most promise for substantially improving the amount of charge stored without causing any of the problems mentioned for solutions (1) and (2).
One previous solution to increase the surface area of the capacitor is to replace common stack capacitor technology with trench capacitors. In common stack capacitor technology, the capacitor is built on a surface created on a semiconductor substrate. In trench capacitor technology, the capacitor is formed in a trench that is fabricated in a semiconductor substrate itself. An increase in depth of the trench, increases the surface area of the capacitor. However, the depth of the trench is limited by present fabrication methods and tools.
Moreover, as the critical dimensions shrink, it becomes more and more difficult to achieve deep trench (DT) structures that would fulfill the cell capacitance requirements for a given generation device. The difficulty of fulfilling cell capacitance requirements is due to severe reactive-ion etching (RIE) lag effects, which are caused using prior art processes. RIE requires reactive ions to reach the bottom of the trench. RIE becomes increasingly difficult when high aspect ratio trenches (greater than 10) are required.
The term “aspect ratio” denotes the ratio between the depth (i.e., height) of the trench and the width of the trench opening.
U.S. Pat. No. 6,025,225 to Forbes, et al. as well as the various references cited therein define the above problem of increasing the surface area of the capacitor in memory cell structures and provide solutions for obviating the same. For example, in the Forbes, et al. disclosure the sidewalls of the etched trench have been roughened. The process disclosed in Forbes, et al. includes deposition of amorphous Si on the trench sidewalls.
U.S. Pat. No. 4,843,025 to Morita, et al. provide a method to form narrow, loop-shaped trenches by (i) depositing epitaxial Si on the bottom of a very wide, rectangular trench; (ii) forming an oxide film on the trench walls of the same thickness as the trench width to be subsequently fabricated; and (iii) etching trenches to leave a narrow moat-like trench.
IBM Technical Disclosure Bulletin VOL. 34, No. 10A, March 1992 to R. S. Bennet, et al. disclose a method of fabricating narrow self-aligned trenches and isolated N-type Si regions with a buried N+ layer. In this disclosure, epitaxial Si, which is grown by conventional procedures, is used over trench dimensions that have an aspect ratio of 1.0.
In view of the above drawbacks with prior art methods for fabricating DT structures, there is a continued need for providing a new and improved method that is capable of forming deep trenches that are independent of the critical DT mask dimensions as defined by lithography. Such a method is especially needed for providing high aspect ratio trenches whose height to width ratio is greater than 10.